Αρχιτεκτονικές υπερβαθμωτών μικροεπεξεργαστών με δυναμικη και εκτός σειράς εκτέλεση εντολών και αξιολόγηση της απόδοσής τους

Δήμητσας, Βασίλειος Π.

Master Thesis

Author

Δήμητσας, Βασίλειος Π.

Date

2012-10-05

Abstract

In the current thesis the architectures of superscalar processors are studied. Superscalar processors are capable of out-of-order instructions’ execution, resolving branches, as well as jumps and determining the correct instruction stream dynamically. The research was focused mainly on IVM processor model. It was designed in University of Illinois, at Urbana-Champaign and it is the only superscalar processor that is freely available to the scientific community. It consists of a 12-stage pipeline and contains all of those characteristics (branch predictor, memory dependence predictor, renaming techniques, prefetching techniques and so on) that classify it in the category of superscalar architectures. Furthermore, there has been an experimental evaluation of IVM by executing several programs, which were implemented in C programming language and in Alpha assembly language. The reader is thus able to comprehend the various aspects of the operation of a superscalar processor. The content of the master thesis is structured as follows: Initially, there is an introductory description of the study which took place during the elaboration of the specific dissertation. The 1st chapter contains a detailed presentation of the organization of superscalar processors and their typical characteristics. In the 2nd chapter the store sets mechanism is described for predicting memory dependences. The 3rd chapter includes a thorough analysis of IVM processor and its pipeline stages. The 4th chapter describes the steps which are necessary in order to simulate a program execution in IVM. The 5th chapter contains the experimental evaluation of the processor. Finally, the thesis ends with the conclusions that were extracted from this research and two appendices. In appendix A the scripts, which are used during the construction of the executable program, are available, and in appendix B Alpha Instruction Set Architecture is briefly described.