Αξιολόγηση της ασφάλειας και της αξιοπιστίας επιταχυντών υλικού σχεδιασμένων με χρήση Σύνθεσης Υψηλού Επιπέδου
Evaluation of the reliability and security of hardware accelerators using High-Level Synthesis
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Keywords
Επιταχυντές υλικού ; Hardware accelerators ; Σύνθεση Υψηλού Επιπέδου ; Ψηφιακά κυκλώματα ; Vivado HLS ; Εισαγωγή σφαλμάτων ; Fault Injection ; Ασφάλεια ; Αξιοπιστία ; Security ; Reliability ; Optimizations ; Βελτιστοποιήσεις ; Αξιολόγηση ; FPGAs ; Αντίμετρα ; Countermeasures ; Exhaustive Single Bit Flip ; SBF ; Εξαντλητική εισαγωγή μονών σφαλμάτων ; Εισαγωγή τυχαίων πολλαπλών σφαλμάτων ; Multiple Bit Flip ; MBF ; statistical sample ; Στατιστικό δείγμα ; RTL ; Επίπεδο μεταφοράς καταχωρητών ; Ενσωματωμένα ψηφιακά κυκλώματα ; Embedded digital circuits ; Redundancy ; Simple Canright Sbox ; Masked Canright HLS ; AES ; Sbox ; C, C++ ; High Level Language (HLL) ; Hardware Description Language (HDL) ; High Level Synthesis (HLS) ; Προσομοίωση ; Simulation ; Evaluation ; Επιταχυντές υλικούAbstract
Most digital media used for the full range of human communications whether personal, social, professional, financial, commercial and other communications involve to a lesser or greater extent digital circuits embedded in various types of devices. It stands to reason that there is a great need to ensure the safety and reliability of digital circuits. It is extremely important where the encryption takes place, as it is unprofitable at software level. For the best possible performance, the processing of these cryptographic functions is chosen to be done by cryptographic accelerators. The evolution of digital circuits has contributed to reducing the size of electronic components and, by extension, the circuits surface area, which are usually manufactured in the form of integrated circuits (ICs) and programmed to perform a series of complex functions. The goal is the production of reliable and secure hardware that will be the component to produce reliable and secure digital circuits. Hardware description languages such as VHDL and Verilog are suitable for designing digital circuits and describe both the behavior and structure of a circuit. However, they are less efficient than high-level languages (High Level Languages (HLL) such as C, C++ and System C. For the circuit’s synthesis, the High-Level Synthesis (HLS) tools, based on the hardware’s description in a high-level language, synthesize the corresponding circuit at the register transfer level (Register Transfer Level - RTL). The generated RTL is in VHDL and/or Verilog compatible with the synthesis flow for the final circuit implementation (FPGA synthesis & implementation). In this thesis, the Vivado High-Level Synthesis tool from Xilinx was used, which supports the simulation and implementation (synthesis) of a model in hardware description language (HDL). It offers the performance of the requested functionality of the hardware (through the enforcement of defined constraints and optimizations) by simulating and automatically creating a composition in a hardware description language which then through a suitable tool leads to hardware implementation with FPGAs or ASICs The design of a digital circuit is modeled with various implementations, with different optimizations (instructions-directives) to study which of all implementations is the most secure and reliable. The reliability and security of the circuits are evaluated with extensive fault injection experiments. From the results, it is determined whether the integration of countermeasures and hardening techniques is needed, to improve circuit’s resilience. For this reason, in this dissertation, we focus on fault injection through simulation in the RTL as it will allow us to study the robustness of the circuits [1] at the beginning of the design flow.