Development of a soft error vulnerability analysis framework for FPGA devices

Αγιακάτσικας, Δημήτριος Σ.

Master Thesis

Author

Αγιακάτσικας, Δημήτριος Σ.

Date

2014-11-24

Abstract

As the features sizes of the FPGA devices are moving aggressively to the nanometer regime, the single-event upsets (SEUs) are expected to become a major reliability concern for the SRAM-based FPGAs. Given the limited information provided by the FPGA vendors about the susceptibility of the FPGA designs to soft errors, the research community requires SEU analysis tools to accommodate the development and assessment of SEU mitigation approaches. On the other hand, open-source CAD tools, such as RapidSmith and Torc, have been recently proposed that target industrial FPGA architectures without escaping the boundaries of proprietary issues in contrast with the traditional open-source FPGA CAD tools. In this thesis, an open-source framework is presented for the soft error vulnerability analysis of Xilinx FPGA devices. The proposed framework will allow researchers to evaluate their reliability-aware CAD algorithms and estimate the soft error susceptibility of the designs at early stages of the implementation flow for the latest Xilinx architectures. Furthermore the well-known simulated-annealing placement algorithm is implemented in RapidSmith - where a limited random placer is currently supported - in order to evaluate the proposed post-placement sensitivity analysis method. To demonstrate the vulnerability analysis framework, a rich set of experiments is carried out. The thesis compares the soft error awareness of different packing/mapping tools (VTR and Xilinx tools) and different place tools (simulated annealing and Xilinx placers). The proposed method is evaluated by correlating its sensitivity analysis results with the Xilinx sensitivity report.