Επιτάχυνση προσομοίωσης με χρήση της τεχνικής FPGA-in-the-Loop
Λουκιανός, Εμμανουήλ Λ.
SubjectField programmable gate arrays -- Design and construction ; System design -- Data processing ; Προσομοίωση
Simulation is an integral part of system development. It is used to test designs under various scenarios and for the improvement of their characteristics. It is also used in designs that are too complicated for analytical solutions. Simulation of simple designs is completed in a few cycles and the required time is relatively short. But not all simulations require a small number of cycles to be completed. In many cases termination criteria of a simulation is based on the processing of a large amount of samples. Such a case is the calculation of BER (Bit Error Rate) of a communication system. To calculate a single point on a BER diagram, a large number of data must be processed. To plot a diagram with BER points up to 10-9, the system must process 109 bits of which only one will be erroneous. To create a plot that contains sufficient points to draw a curve, many hours would be required. Hardware Co-Simulation can accelerate significally this procedure. Considering the parallel nature of FPGA devices, by implementing some parts of the model in hardware, simulation time can be reduced substantially. Hardware Co-Simulation can make it possible to complete simulation of complex designs in a much shorter period of time. Many factors define the acceleration of simulation time by using the FPGA-in-the-Loop technique. In this thesis, simple and complex designs are being put to test in order to estimate the benefit that hardware Co-Simulation can attribute. The tools and the models used are also presented.