Υλοποίηση μιας περιορισμένης μηχανής Boltzmann με την τεχνική FPGA-in-the-Loop
Implementation of a restricted Boltzmann machine using FPGA-in-the-Loop technique
Πασχάλης, Δημήτριος Π.
KeywordsΜηχανική μάθηση ; Τεχνητά νευρωνικά δίκτυα ; Προσομοίωση ; Restricted Boltzmann Machines ; Field Programmable Gate Arrays
One of the fields of computer science that flourishes these last years is that of Machine Learning. The field grows rapidly and is enhanced with new techniques and technologies. By developing stronger algorithms, past difficulties are overcome and is now possible to solve complicated problems that previously seemed impossible. One such algorithm is that of Restricted Boltzmann Machines, which are a type of Artificial Neural Network. Such networks are used to build even greater neural networks, the so called Deep Belief Networks, which provide the best technique for solving difficult Machine Learning problems. They are mainly developed in Matlab environment and other such kinds of software. These kinds of networks, though, are highly demanding in resources and usually require a great amount of time for proper training. That is the main reason that prohibits their use for immediate commercial or industrial applications. As a result the field has been enriched with researchers from the fields of Digital Design and Computer Architecture that cooperate with researchers from the field of Artificial Neural Networks trying to design hardware, capable of executing such calculations and achieve better efficiency as well as reducing the execution time. Furthermore FPGA and GPU designs have been proposed that, despite of some restrictions, have made noteworthy progress paving the way for more researchers to follow. FPGAs (Field Programmable Gate Arrays) are generall purpose integrated circuits capable of programming. Parallelism in FPGAs is inherent and they are oftenly used as a means to speed up applications. Part of computations, specifically of parallel nature, can be transferred to hardware level providing better execution time (hardware acceleration). This leads to applications that share computations between general purpose processors (Software) and FPGA (Hardware) for maximum efficiency. On such technique for this kind of applications is FPGA In the Loop. The purpose of this project is to propose an alternative way for executing the functions of a Restricted Boltzmann Machine, by using Matlab Simulink and FPGA In the Loop technique and achieve Hardware Software Co-Simulation. We aim to create a framework, by the use of design techniques, which makes the transfer of the calculations to the hardware level possible and can be used with different parameters according to each specific Restricted Boltzmann Machine design.