Σχεδίαση και υλοποίηση σε FPGA του μικροεπεξεργαστή PicoBlaze με την τεχνική Triple Modular Redundancy
Master Thesis
Date
2011-09-28View/
Subject
Field programmable gate arrays -- Design and construction ; System design -- Data processing ; Integrated circuits -- Very large scale integration ; Σχεδιασμός συστημάτωνAbstract
The objective of this thesis is to present the Triple Modular Redundancy (TMR) technique, in theory and in practice. Initially, several fault tolerant techniques are described, and the impact of upsets in various applications is discussed. A detailed description of the TMR method is given as well as of the PicoBlaze microcontroller, which is the CPU that was adapted according to Xilinx’s suggestions for the Triple Modular Redundancy implementation. The steps that resulted in the accomplishment of this goal are thoroughly described. Then, we inject both permanent and temporary faults in the TMR-version of PicoBlaze to prove its fault-tolerant capability. Also, we calculate the impact of Triple Modular Redundancy on the FPGA-based PicoBlaze in terms of performance and device resources utilization. Finally, future implementations are suggested.
Language
GreekCollections
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Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 4.0 Διεθνές
Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 4.0 Διεθνές