Μεθοδολογίες δοκιμής για πολυεπεξεργαστές και πολυπύρηνα ολοκληρωμένα κυκλώματα
Doctoral Thesis
Date
2010-05-28View/
Abstract
This PhD thesis proposes methodologies for self-testing problem of System-on-Chip, SoC and especially for communication controllers of these integrated circuits, as well as for symmetric multiprocessors with different interconnection schemes such as shared bus and crossbar switch. In the first chapters of this thesis we proposed a systematic self-testing methodology for communication peripheral controllers integrated in a SoC. The proposed methodology is based on deterministic testing and is generic and fully applicable in any communication peripheral. Moreover, we proposed a hybrid self-test methodology for SoC that combines the deterministic methodology with a semi-automated, pseudorandom methodology. In the second part of this thesis we presented a test routines scheduling methodology for symmetric multiprocessors with different interconnection schemes, such as shared bus and crossbar switch. The solution that we proposed has significant importance nowadays where chip multiprocessors, including either multiple cores (multicores), or multiple threads (multithread) are used more widely than ever. The test scheduling methodology uses the inherent parallelism of multiprocessors architecture in order to decrease dramatically the total test execution time of the self-test programs.
Language
GreekCollections
Except where otherwise noted, this item's license is described as
Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 4.0 Διεθνές
Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 4.0 Διεθνές