Design of a clock fault Injection circuit (clock glitcher) on an FPGA chip
Σχεδίαση κυκλώματος εισαγωγής σφαλμάτων ρολογιού σε ένα FPGA τσιπ
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Keywords
Fault injection ; Clock glitching ; Digital design ; AutomationAbstract
Digital systems are the foundation of modern technology, and their reliability and security are
critical in domains such as IoT, aerospace, automotive, and defence. Fault injection is a
powerful technique for evaluating the resilience of such systems by deliberately disturbing their
normal operation. Among the available methods, clock glitching is one of the most effective,
offering low cost and fine control over fault parameters.
This thesis investigates FPGA-based clock glitching with a focus on precision, reproducibility,
and adaptability. Using the Xilinx Arty Z7-20 platform, we design and implement a
hardware/software co-design architecture that leverages Mixed-Mode Clock Managers
(MMCMs), the Dynamic Phase Shift Interface (DPSI), and input delay elements (IDELAY) to
create controlled glitches. By combining these FPGA primitives with automated testing via the
Zynq Processing System and UART-controlled software, the proposed system enables fine-
grained exploration of glitch coordinates and repeatable fault injection campaigns.
Experimental evaluation was conducted on basic sequential elements such as accumulators
and flip-flops. Results demonstrate that controlled glitching can consistently induce specific bit
faults, with success rates exceeding 60% under optimized conditions. Placement and routing
were shown to significantly affect outcomes, highlighting the importance of physical design in
both attack effectiveness and reliability testing.
The contributions of this work are fourfold: (i) a practical methodology for FPGA-based clock
glitching with sub-cycle resolution, (ii) a comparative analysis of MMCM- and IDELAY-based
approaches, (iii) an experimental study of glitch effects on digital building blocks, and (iv) an
automated hardware/software framework for reproducible large-scale testing.
These findings confirm that FPGA-driven clock glitching is a cost-effective and flexible
technique for fault analysis. Beyond testing, the proposed methodology can inform both the
development of more resilient digital systems and the design of countermeasures against
malicious fault injection attacks.
Department
Σχολή Τεχνολογιών Πληροφορικής και Επικοινωνιών. Τμήμα ΠληροφορικήςNumber of pages
38Language
EnglishCollections
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Αναφορά Δημιουργού-Μη Εμπορική Χρήση 3.0 Ελλάδα
Αναφορά Δημιουργού-Μη Εμπορική Χρήση 3.0 Ελλάδα