Τεχνικές εισαγωγής, ανίχνευσης και διόρθωσης προσωρινών σφαλμάτων σε προγραμματιζόμενες συσκευές λογικής Xilinx Virtex-5
Τσώνη, Παναγιώτα Ε.
SubjectDigital integrated circuits -- Design and construction ; Logic design ; Microelectronics ; Electric discharges
Single Event Upsets (SEUs) are transient faults that appear in semiconductor devices. SEUs occur when charged particles hit the silicon transferring enough energy in order to provoke a fault in the system. The main consequences of the transient effect are ψηφίο flips in the memory elements. SEUs have been constantly magnified the last years, due to the continuous technology evolution that has led to highly complex architectures, which integrate a large amount of embedded memories, followed by an amazing downscaling of transistor feauture sizes. So protecting integrated circuits against upsets has become imperative need. For that reason, researchers have proposed fault tolerant techniques that maintain the reliable operation of ICs despite the existence of upsets. Our aim was to create an application, in which we could implement SEUs and observe the reaction of the device. The application consists of two different circuits. The first one combines an SEU Controller macro from XILINX and a soft core called PicoBlaze and it is responsible for injecting, detecting and correcting SEUs in the device. The second circuit is the main application and combines a second PicoBlaze with an LCD Controller. The circuit is responsible for shifting a message to the LCD display of the device and it is the main area that the SEUs are taking place. The application implemented in an FPGA device from XILINX (VIRTEX-5 ML505) and we injected SEUs at specific locations of the configuration map and then observe the reaction and the critical areas of the design.